Pay Range: $50/hr-$55/hr, the pay rate may differ depending on your skills, education, experience, and other qualifications.

Featured Benefits:

• Medical Insurance in compliance with the ACA
• 401(k)
• Sick leave in compliance with applicable state, federal, and local laws

Job Description:

• Digital logic design experience in Verilog/System Verilog
• Experience in developing unit level test benches with Verilog/System Verilog
• Experience with simulation tools like VCS and Modelsim
• Knowledge of industry standard Memory Mapped and Streaming protocols including AMBA AXI protocols.
• Familiarity with network-on-chip (NoC) topologies and design methodology.
• Experience in FPGA design and familiarity with FPGA design tools – Intel FPGA Quartus, Xilinx Vivado, Vitis etc.
• Experience in timing closure for high speed FPGA designs
• Knowledge of scripting in tcl, perl or python.
• FPGA design experience required, preferably Xilinx FPGAs. Experience with going through 3-5 large FPGAs through complete design cycle, from RTL to timing driven synthesis to place & route, static timing analysis.
• 5+ years of RTL, – Verilog, System – Verilog, – VHDL experience 5+ years of FPGA design experience, preferably Xilinx FPGAs. Comfortable with C, expertise with Symplify, – VCS, Modelism and Xilinx ISE tool Experience with USB, microprocessor, SDIO/SD/eMMC, Audio at RTL level will be plus Logic analyzer, PCB/hardware bring up and debug will be plus.
• Protocol level RTL implementation knowledge on USB/OTG, PCIe, eMMC, SDIO/SD, ARC or some microcontroller, SPI, DDR2 memory. Expert in computer architecture and some understanding on PCB board level hardware
• Minimum Educational Requirement: Bachelors, masters preferred- Computer Engineering, Electrical Engineering, Electronics Engineering.